Initializing gui preferences from file  /var/home/ms3xy/.synopsys_icc_prefs.tcl
icc_shell> gui_start
Information: Visibility is turned ON for cells and cell contents because the task is set to Block Implementation (GUI-026)
icc_shell> source ../scripts/setup.tcl
icc_shell> source ../scripts/definitions.tcl
Start to load technology file ../ref/techfiles/saed90nm_icc_1p9m.tf.
Information: Non-metal layer 'DIFF_33' has the metal layer attribute 'endOfLineCornerKeepoutWidth'. (line 1613) (TFCHK-046)
Warning: DesignRule attribute 'layer2' is assigned a non-physical layer 'DNW'. (line 1987) (TFCHK-079)
Warning: DesignRule attribute 'layer2' is assigned a non-physical layer 'RPOLY'. (line 2190) (TFCHK-079)
Warning: Layer 'M1' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.33. (TFCHK-049)
Warning: Layer 'M2' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M3' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M4' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M5' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M6' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M7' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M8' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.465 or 0.5. (TFCHK-049)
Warning: Layer 'M3' has a pitch 0.32 that does not match the doubled pitch 0.64 or tripled pitch 0.96. (TFCHK-050)
Warning: Layer 'M4' has a pitch 0.32 that does not match the doubled pitch 0.64 or tripled pitch 0.96. (TFCHK-050)
Warning: Layer 'M5' has a pitch 0.32 that does not match the doubled pitch 0.64 or tripled pitch 0.96. (TFCHK-050)
Warning: Layer 'M6' has a pitch 0.32 that does not match the doubled pitch 0.64 or tripled pitch 0.96. (TFCHK-050)
Warning: Layer 'M7' has a pitch 0.32 that does not match the doubled pitch 0.64 or tripled pitch 0.96. (TFCHK-050)
Warning: Layer 'M8' has a pitch 0.32 that does not match the doubled pitch 0.64 or tripled pitch 0.96. (TFCHK-050)
Warning: Layer 'M9' has a pitch 0.9 that does not match the doubled pitch 0.64 or tripled pitch 0.96. (TFCHK-050)
Technology file ../ref/techfiles/saed90nm_icc_1p9m.tf has been loaded successfully.
Loading db file '/net/redfox.ece.Virginia.EDU/isan0/users/ms3xy/Desktop/synopsys/syn_tut/icc_project/ref/models/saed90nm_typ_ht.db'
Warning: Conflict unit found: MW tech file capacitance unit is pF; Main Library capacitance unit is fF. (IFS-007)
Warning: Conflict unit found: MW tech file resistance unit is kOhm; Main Library resistance unit is MOhm. (IFS-007)
Loading db file '/app/synopsys/icc/F-2011.09-SP2-1/libraries/syn/gtech.db'
Loading db file '/app/synopsys/icc/F-2011.09-SP2-1/libraries/syn/standard.sldb'
Type of creating bus for undefined cells : 0

*****  Verilog HDL translation! *****

*****    Start Pass 1 *****

*****  Pass 1 Complete *****
Elapsed =    0:00:00, CPU =    0:00:00

*****  Verilog HDL translation! *****

*****    Start Pass 2 *****

*****  Pass 2 Complete *****

*****   Verilog HDL translation completed! *****
Elapsed =    0:00:00, CPU =    0:00:00
Specified top module (fsm_plant_opt) not found in verilog source file.
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'clk'. (UID-109)
Error: Value for list 'clock_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'clk'. (UID-109)
Error: Value for list 'clock_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
icc_shell> 